Field
The present disclosure relates to the design of a deskew first-in, first-out (FIFO) buffer. More specifically, the present disclosure relates to the design of a FIFO buffer having simplified initialization.
Related Art
Modern ASIC and CPU designs are often partitioned into multiple communicating clock domains. The throughput and latency of the synchronizing blocks that form the interfaces between these clock domains can be critical for overall performance and robust operation. Often, these clocks are generated from the same source and have the same fundamental frequency but an unknown phase offset because of the partitioning of the design. In other cases, the clock frequencies may have known rational ratios. In these cases, mesochronous (matched frequency) implementations can accommodate unknown or large clock skews with the advantage that metastable behavior is excluded after initialization.
In one existing circuit, a single-stage, handshaking first-in, first-out (FIFO) is used as an efficient mesochronous interface. However, it may be difficult to adopt this existing circuit in typical design flows. In particular, the existing circuit may use custom, dynamic logic to implement edge-triggered C-elements. Moreover, the initialization procedure used with the existing circuit may involve continuously sweeping the power supply voltage to the interface. Furthermore, the existing circuit may be limited to a single FIFO stage. While this architecture may be sufficient to accommodate arbitrary phase offsets for a wide variety of applications, it may not be able to tolerate substantial drifts in skew during the operation of the interface.
Hence, what is needed is an interface for use between clock domains without the above-described problems.